Computer technology continues to advance at a remarkable pace, with numerous improvements being made to the performance of both processors—the “brains” of a computer—and the memory that stores the information processed by a computer.
One aspect of computer technology that can have a significant impact on system performance is the communication between various components in a computer or other data processing system. The communications between components such as processors, memory devices, processing complexes (sets of interconnected processors and memory devices), peripheral devices, and even separate computers, can have a significant effect on the overall performance of a computer system. Moreover, even from the perspective of individual components, and the various sub-components that may be disposed on the same or separate integrated circuit chips, the manner in which data is communicated within a computer system is often a significant contributor to the speed and computing power of the system.
For example, one prevalent architecture utilized to connect memory devices to a processor is a multidrop bus architecture, where a plurality of address and data lines are routed between a processor or intermediate memory controller to a plurality of memory devices. The various lines in the bus essentially couple the memory devices in parallel with one another, and each device receives the same signals. Typically, shared bus architectures of this type, despite improvements in terms of greater width (number of address and/or data lines) and data transmission rates, have been hampered by a number of drawbacks. First, the parallel nature of the architecture, and the resulting signal alignment issues that are raised by communicating data in a parallel fashion, have become limiting factors on the overall performance of the architecture. Moreover, the aforementioned issues also place limits on the lengths of the interconnects, and thus the types of connectors and form factors that are supported. Furthermore, these architectures are characterized by relatively high connector counts, thus requiring a high number of signal paths between devices.
One relatively recent memory architecture that has been utilized to address some of the shortcomings of a shared bus architecture involves the use of point-to-point interconnects between multiple nodes or components in a data processing system. Often, the point-to-point interconnects utilize serial transmission as opposed to parallel transmission, which can reduce the number of interconnects, while providing comparable or greater transmission speed due to the elimination of many of the signal alignment issues raised by parallel architectures. Some point-to-point architectures rely on complex switching to route data to desired components or nodes; however, other point-to-point architectures rely on individual nodes or components to forward data intended for other components coupled to the architecture.
In many applications, the use of point-to-point interconnects provides comparatively greater performance, as well as reduced connection counts and greater flexibility in terms of interconnecting components or nodes coupled to the architecture. Moreover, through the use of redundant connections, greater reliability may be provided, whereby the failure of a connection or a particular node may be overcome by routing data communications around a failed node.
As noted above, while some point-to-point architectures rely on complex switching or redundant connections, other point-to-point architectures desirably omit comparable data routing functionality to reduce complexity and cost, and to increase overall performance in some applications.
One such architecture is often referred to as a daisy chain architecture, where a sequence of nodes or components are interconnected by means of point-to-point interconnects coupled between adjacent nodes in the system. Often, the point-to-point interconnects comprise pairs of unidirectional interconnects, with one unidirectional interconnect used for communicating data in one direction between the adjacent nodes, and the other interconnect used to forward data in the opposite direction between the nodes. In such a configuration, the unidirectional interconnects form two unidirectional communication links, ensuring the data can be communicated between any two nodes in the architecture.
Incumbent in a daisy chain architecture is a capability within each node for forwarding data destined for a subsequent node in the architecture to the next adjacent node. In this regard, many daisy chain architectures provide driver circuits that essentially relay or repeat received signals and forward such signals as necessary to the next node in the architecture.
One specific example of a daisy chain architecture is implemented in the fully buffered dual inline memory module (FB-DIMM) memory architecture, for which a formal specification has been established by the Joint Electron Device Engineering Council, (JEDEC) of the Electronic Industry's Alliance (EIA). The FB-DIMM specification defines a high speed serial interface in which a memory controller is coupled to an FB-DIMM, upon which is disposed multiple memory devices and a controller device incorporating an interface between the memory devices and the high speed serial interface. The controller device also includes driver circuitry for repowering received signals and passing those signals along to the next FB-DIMM in the chain.
As with other memory controller designs, many FB-DIMM memory controllers support multiple memory channels, whereby separate daisy chain arrangements of FB-DIMM's are coupled to each memory channel, permitting the memory channels to operate independently and in parallel with one another.
The high speed serial communication links between the components in an FB-DIMM architecture include separate unidirectional read and write channels made up of sets of differential signal pairs, and over which data and address information is passed. Separate clocking and control buses are also provided, but not implemented using point-to-point interconnects.
It has been found, however, that a conventional daisy chain architecture such as the FB-DIMM architecture is not readily suited for use in some high availability applications. In particular, one benefit of a conventional shared bus architecture is ability to provide “hot” replacement or swapping of individual devices in an architecture. For example, some conventional shared bus memory architectures support the ability to remove and replace individual memory devices while a system is running, and without requiring the system to be shut down. In such circumstances, power is typically removed from an individual device, the device is physically removed from its connector (e.g., a slot for a memory device disposed on a module or card), a new device is inserted into the connector, and power is applied to the new device. So long as the system logic avoids attempts to access the device being replaced during the replacement procedure, other devices may continue to be accessed during the procedure, thus ensuring continued system availability. Furthermore, since the devices are essentially coupled in parallel via a shared bus, and all signals are propagated to all devices, the unavailability of one particular device does not interrupt the communication of signals to other devices.
A daisy chain architecture such as FB-DIMM, on the other hand, relies on individual components (here each FB-DIMM) to forward signals received from previous components in the chain to subsequent components in the chain. As such, an individual FB-DIMM could not be powered off and removed from the system without causing a discontinuity in high speed serial interface that would prevent data from being communicated between the memory controller and any subsequent FB-DIMM's in the daisy chain.
As a result, conventional FB-DIMM and other daisy chain configurations may not be suitable for use in applications where high availability is desired.